Typical flash memory devices contain a nonvolatile memory cell array for random access data storage. Some prior flash memory devices also include a write control circuit for programming and erasing the memory cell array.
Prior flash memory devices may employ an on-chip data buffer to increase programming throughput of the flash cell array. The data buffer enables increased programming speed by buffering programming data. The data buffer enables fast access to the programming data by the write control circuit. The fast access to the programming data enables the write control circuit to amortize the cycling of program level voltages across multiple bytes in the flash cell array.
In such prior flash memory devices, a user typically provides an input/output driver that loads programming data into the data buffer. The input/output driver then issues a program command to the write control circuit. Thereafter, the write control circuit accesses the data within the data buffer and uses that data to program the flash cell array. The input/output driver can load another block of data into the data buffer only after the write control circuit completes programming, and is no longer accessing the data buffer.
In such prior flash memory devices, because the data buffer is not accessible by the input/output driver while the write control circuit is accessing the data buffer, the input/output driver idles while waiting for the write control circuit to complete the program operation. The idle time of the input/output driver reduces programming throughput and data throughput of the flash memory device.